The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a simplified test pattern.
Generally, semiconductor memory devices include a plurality of memory cells provided with one group of memory cells for which data are inputted/outputted via a bit line BL and the other group of memory cells for which data are inputted/outputted via a complementary bit line, i.e. a bit line bar BLB.
FIG. 1 is a block diagram illustrating connections of bit line pairs BL and BLB and word lines WL in a cell array of a conventional semiconductor memory device. FIG. 1 illustrates a cell array structure of a typical semiconductor memory device, which is called a folded bit line structure
In the typical semiconductor memory device, a word line WL is selected by an X address and a bit line sense amplifier BLSA is assigned by a Y address, so that data of a memory cell are inputted/outputted to/from memory cells. In FIG. 1, memory cells of zeroth, third, fourth and seventh word lines WL0, WL3, WL4 and WL7 are connected to bit lines BL, and memory cells of first, second, fifth and sixth word lines WL1, WL2, WL5 and WL6 are connected to complementary bit lines BLB. In the typical semiconductor memory device, when an external data is ‘0’, i.e., a logic low level, data ‘0’ is written to the memory cell connected to the bit line BL, but data ‘1’ (a logic high level) is written to the memory cell connected to the complementary bit line BLB.
Even though the same data is inputted from the outside, data actually written to a memory cell may become different depending on its address. That is, the written data is in phase or out of phase with the inputted data according to the address. This inconsistency of the data phase according to the address also occurs in a structure where a data input/output line of the bit line sense amplifier BLSA is provided in pair, for example, an open bit line structure, as well as the folded bit line structure of FIG. 1.
FIG. 2 illustrates a block diagram of a conventional semiconductor memory device. The conventional semiconductor memory device, which performs read/write operations of data from/to a memory cell, includes an address buffer, a state machine, an X address block, a Y address block, a row address strobe (RAS) logic, a column address strobe (CAS) logic, an X decoder, a Y decoder, a data transfer block, a write driver WDRV, an input/output sense amplifier IOSA, a bit line pair BL and BLB, and a word line WL.
The address buffer is configured to receive an address. The state machine is configured to decode a command. The write driver WDRV transfers data of a global input/output line GIO to a local input/output line LIO in a write operation. The input/output sense amplifier IOSA transfers data of the local input/output line LIO to the global input/output line GIO in a read operation. The bit line pair BL and BLB is connected to a bit line sense amplifier BLSA and memory cells storing data. The word line WL controls a gate of the memory cell. The read/write operations of data in the conventional semiconductor memory device is well known to a person of ordinary skill in the art, and hence further detailed description for them will be omitted herein.
FIG. 2 illustrates only four memory cells for simplicity, in which two memory cells are connected to the bit line BL and the other two memory cells are connected to the complementary bit line BLB. When the external data ‘0’ is inputted through a DQ pin in an embodiment of FIG. 2, an in-phase data, i.e., ‘0’, is written to the memory cell connected to the bit line BL but an out-of-phase data, i.e., ‘1’, is written to the memory cell connected to the complementary bit line BLB.
According to the conventional memory device as described above, the data, which is identical or inverse to the external data, may be written to the memory cell depending on which memory cell the data is written to, that is, depending on which memory cell the data is written between the memory cells connected to the bit line BL and the complementary bit line BLB. Therefore, the checking of data pass/fail in a testing procedure should always be performed in consideration of the relation with the address, which makes it difficult to perform the analysis.